1. Field of the Invention
The present invention relates to a lateral MOSFET and a manufacturing method thereof and, more particularly, to a double diffused lateral MOSFET (insulated-gate field effect transistor) applicable to a high withstand-voltage Bi-CMOS and manufacturing method thereof.
2. Description of the Related Art
In general, when a double diffused lateral MOSFET is composed of complementary MOS (CMOS), either a p-channel MOS transistor or an n-channel MOS transistor is formed as a lateral MOSFET.
FIG. 1A shows a pattern layout of a conventional lateral p-channel MOS transistor, and FIG. 1B is a sectional view taken along a line B--B of FIG. 1A. In FIGS. 1A and 1B, numeral 50 denotes an n.sup.- -type semiconductor substrate; 51, a p-type diffused layer for drain region; 52, a p.sup.+ -type diffused layer for drain electrode connecting layer; 53, an n-type diffused layer for channel and back gate regions; 54, a p.sup.+ -type diffused layer for source region; 55, a gate insulating film; 56, a gate electrode; 57, an interlayer insulating film; 58, a drain electrode; and 59, a source/back gate common electrode. The pattern is designed so that the gate electrode 56 may invariably exist between the contact portion 59a of the source/back gate common electrode 59 and drain contact portion 58a.
In such a conventional lateral MOSFET, when an electrostatic surge of high-voltage enters the drain electrode 58, a surge current flows in the forward direction of the parasitic diode, as shown by the arrow in FIG. 2. In other words, the surge current flows through the path from the p-type diffused layer 51 as the drain region to the n-type diffused layer 53 as the channel and back gate regions. At that time, an electric potential of the p-type diffused layer 51 increases due to the resistance R of the n-type diffused layer 53. A breakdown of the gate insulating film 55 occurs when the increased potential exceeds its dielectric strength. Thus, an electrostatic breakdown of the device also occurs.